The present invention relates to a buffer circuit with transfer means for transferring a logic signal received at its input to its output, with the transfer means comprising at least one logic gate having a trip point sensitive to the supply voltage of the buffer circuit.
In integrated circuits, external logic signals are often received through buffer circuits that shape the signal. Such buffer circuits generally comprise logic gates having a trip point sensitive to the variations in the supply voltage applied to the integrated circuit. Certain operations sometimes prompt a substantial current draw in the output state of the integrated circuit leading to a temporary but significant drop in the supply voltage. A supply voltage drop of this kind leads to a drop in the tripping threshold of the buffer circuits. This drop gives rise to the transmission of erroneous signals, as will be understood more clearly by the following example.
FIG. 1 illustrates an integrated circuit 1 on an interconnection support 10. The integrated circuit 1 has contact zones P1 to P5 connected to zones P1xe2x80x2 to P5xe2x80x2 of the support 10 by ultrasonically soldered metal wires 11. The zone P1 receives a ground potential GND, the zone P2 receives the supply voltage VCC, the zone P3 receives an external clock signal CLKEXT, the zone P3 is designed to receive data DTR, and the zone P5 is designed to send data DTX.
Due to the resistivity of the wires 11 and their parasitic inductance, the ground potential GND present at the zone P1, under the conditions described below, may be different from the external ground potential GNDEXT present at the zone P1xe2x80x2. Similarly, the supply voltage VCC received at the zone P2 may be different from the external supply voltage VCCEXT present at the zone P2xe2x80x2.
The external clock signal CLKEXT received at the zone P3 is applied to the core 2 of the integrated circuit (represented schematically by a block) by a buffer circuit 3 comprising two cascade-connected inverter gates 4, 5 whose output delivers an internal clock signal CLK that copies the variations of the external clock signal CLKEXT.
The data DTX sent by the core 2 of the integrated circuit are delivered to the zone P5 by an output buffer 6 comprising two cascade-connected inverter gates 7, 8. The output inverter gate 8 comprises a large-sized pull-up transistor 8-1 capable of delivering high current when sending a 1 in the presence of a highly capacitive load. Similarly, the gate 8 comprises a large-sized pull-down transistor 8-2 capable of receiving substantial current during the sending of a 0 (GND) in the presence of a highly capacitive load. A capacitive load of this kind is, for example, a data bus connected to the zone P5xe2x80x2, having a high parasitic capacity.
Thus, when the integrated circuit 1 sends data on the zone P5, in the presence of a highly capacitive load, the high current that is output during the transmission of a 1 leads to a drop in voltage in the supply wire 11 connecting the zone P2 to the zone P2xe2x80x2, and the reduction of the internal supply voltage VCC in relation to the external voltage VCCEXT. Similarly, the high current that is input during the transmission of a 0 causes a drop in voltage in the supply wire 11 connecting the zone P1 to the zone P1xe2x80x2, and an increase in the internal ground potential GND in relation to the external ground GNDEXT.
In synchronous data transmissions, the sending of data is generally synchronized with the clock edges, generally the trailing edges, so that a fluctuation of this kind in the internal supply voltage VCC or the ground potential GND occurs simultaneously with the reception of an edge corresponding to a variation of the external clock signal CLKEXT.
FIGS. 2A to 2D illustrate the consequences of a drop in the voltage VCC when a trailing edge is received from the clock signal. FIG. 2A shows the clock signal CLKEXT received on zone P3 at the time of a trailing edge, and FIG. 2D shows a clock signal CLK delivered by the output of the buffer 3. FIG. 2B shows data DTX sent by the zone P5, and FIG. 2C shows the internal supply voltage VCC received by the zone P2. In FIG. 2A, the line of dashes represents the trip point Vt of the inverter gates 4, 5 which is generally equal to VCC/2.
At the instant t0, the clock signal CLKEXT shows a trailing edge and starts diminishing. At an instant t1, the clock signal CLKEXT reaches the trip point of the gates 4, 5 so that the output of the buffer 3 trips, and the clock signal CLK also goes to 0. The passage to 0 of the clock signal CLK activates the sending of data, herein data at 1 (FIG. 2B), and the sending of data prompts a significant drop in the voltage VCC (FIG. 2C).
It follows that the trip point Vt of the gates 4, 5 also drops (FIG. 2A) and becomes lower than the clock signal CLKEXT at an instant t2, so that the gates 4, 5 again trip. The clock signal CLK delivered by the buffer 3 thus goes to 1 whereas it should have stayed at 0. At an instant t3, the supply voltage VCC rises again, the trip point Vt rises and becomes higher than the clock signal CLKEXT, and the clock signal CLK goes back to 0.
Ultimately, after the passage to 0 of the external clock signal CLKEXT, a short-duration parasitic signal appears at the output of the buffer circuit 3. This parasitic signal risks being processed by the integrated circuit as a clock pulse, leading to errors of operation, such as the sending of data before the xe2x80x9ctruexe2x80x9d trailing edge following the external clock signal appears, for example.
In the prior art, there are known ways of avoiding this problem by making input buffers using inverter gates with switching hysteresis, generally inverter Schmitt triggers. Schmitt inverters of this kind have a low-state trip point or tripping threshold Vtl and a high-state tripping threshold Vth that are distinct, the former being lower than the latter.
However, according to observations made by the Applicant, Schmitt inverters cannot totally eliminate the risk of transmission of parasitic signals. This is shown in FIGS. 3A to 3D which show the appearance of the signals of FIGS. 2A to 2D when the input buffer 3 comprises two cascade-mounted Schmitt inverters. It can be seen that a major drop in the supply voltage VCC (FIG. 3C) following the transmission of data at 1 (FIG. 3B) can also cause the high-state trip point Vth of the Schmitt triggers to drop, at the instant t2, below the level of the clock signals CLKEXT (FIG. 3A). Thus, the internal clock signal CLK herein also has a parasitic pulse which disappears at the instant t3 when the low state trip point Vt1 of the Schmitt inverters become higher than the external clock signal CLKEXT.
In view of the foregoing background, an object of the present invention is to provide a buffer circuit that is not sensitive to a drop in the supply voltage taking place after a leading and/or trailing edge of a signal is received at its input.
This and other objects, advantages and features of the present invention are provided by a buffer circuit comprising means for the transfer, to its output, of the logic signal received at its input, with the transfer means comprising at least one logic gate having a trip point sensitive to the supply voltage of the buffer circuit. The buffer circuit further comprises means to deliver an inhibit signal of a determined duration when the logic signal has a trailing edge and/or a leading edge, means for inhibiting the transfer means by insulating the output from the input of the buffer circuit when the inhibit signal is delivered, and storage means for holding at the output of the buffer circuit the logic value that is present therein when the inhibit signal is delivered.
According to one embodiment, the means for delivering the inhibit signal comprises a delay line receiving a reference signal at its input, and a logic gate receiving at a first input the output of the delay line and at a second input the reference signal. The reference signal has the same trailing and/or leading edges as the logic signal. According to another embodiment, the means for delivering the inhibit signal receives a reference signal at its input, with the reference signal being taken at the output of the buffer circuit.
According to yet another embodiment, the transfer means comprises a first inverter gate and a second inverter gate in series, and the inhibiting means comprises a first switch between the two inverter gates. According to another embodiment, the storage means comprises a third inverter gate receiving the output of the second inverter gate at its input, and the output of the third inverter gate is connected to the input of the second inverter gate by a second switch. The first and second switches may be driven by inverter signals so that the first switch is closed when the second switch is open, and vice versa.
According to another embodiment, the buffer circuit comprises means to block the means delivering the buffer circuit inhibit signal.
The present invention also relates to an electronic circuit comprising at least one buffer circuit as defined above, having its input connected to a terminal of the electronic circuit designed to receive a clock signal.
According to one embodiment, the electronic circuit comprises means to send data in synchronization with trailing edges and/or leading edges of the clock signal. According to another embodiment, the electronic circuit comprises a memory array and means for the transmission, in synchronization with trailing and/or leading edges of the clock signal, of data read in the memory array. The buffer circuit inhibit signal may be sent only during periods of data transmission.